Generally, semiconductor wafers are produced using photolithography, deposition, etching, damascene and polish steps to form circuitry and conductive layers surrounded by dielectric materials to produce a plurality of integrated circuit dies on a semiconductor wafer.
In conventional semiconductor processing, typically, copper or aluminum conductor layers are formed and patterned as “top level metal” connectors within layers lying above the semiconductor substrate. The substrate, which for this discussion includes semiconductor over insulator or other epitaxial or grown layers, typically has transistors or other devices formed with doped regions that provide p-n or n-p junctions. The transistors are often planar MOS devices and in many processes, complementary MOS devices are formed by providing a p type substrate, N type MOS devices are formed in the substrate, N-wells are formed in the substrate and P type MOS devices are formed in the wells. These devices are frequently paired to form CMOS inverters, which as is known in the art, may be coupled to form logic gates, registers, memories, processors and other functions needed to form an advanced integrated circuit.
To complete the integrated circuit, electrical connections are formed using dielectrics, including without limitation high K and low K dielectric materials, as well as oxides, nitrides, and other dielectrics known to those skilled in the art, and metallization layers separated by the insulating layers. The metal layers are patterned as conductive lines. Vias are used to vertically couple these conductors. The conductors may be formed of aluminum and its alloys, copper and its alloys, and other conductive materials. If aluminum is used for conductors, a deposit, pattern, and etch process is used to form the conductors. If copper is used, a single or dual damascene process using a film deposition, photolithography, etch and chemical mechanical process (CMP) to remove excess material over the filled trenches may be used. Presently, copper or an alloy of copper is often used with single and dual damascene processes.
The etching process used in the conventional back end of the line (BEOL) metallization and patterning steps will damage film quality. This impacts, among other objective reliability criteria, the TDDB. Conventional approaches to improve the film quality after etch include photoresist (PR) trimming, CD shrinkage and others. These process improvements usually involve polymerizing using etch techniques and therefore are subject to etching profile damage. Critical dimension uniformity (CDU) will also be impacted negatively by these steps. For improving process TDDB, CD shrinkage from, or with PR trimming are usually used. However the capabilities of the photolithography process remain a bottleneck for advanced semiconductor process technology.
FIG. 1 depicts, in a cross sectional view, an intermediate stage of a conventional BEOL copper semiconductor process. In FIG. 1, a metal layer 101 is shown that was previously formed by, for example, typical copper metallization steps such as electro-deposition and CMP over a semiconductor substrate (not shown). An etch stop layer (ESL) 103 is shown overlying the metal layer 101. This ESL layer will be used to stop etch processes above the metal layer 101 in subsequent process steps. Overlying the ESL layer 103 is a dielectric layer 105. Presently, so-called low-K dielectric materials may be used. Low-K dielectrics have a dielectric constant lower than that of silicon dioxide (about 3.5). Recently, extreme low-K or ELK materials are also being used; these have a dielectric constant below 2.0. Alternative dielectric materials include oxides, nitrides, and even high-K dielectrics, but low-K materials are preferred presently for insulation between the metal layers.
Overlying the dielectric layer 105 is a layer of dielectric anti-reflective coating (DARC) 107. DARC is used to prevent unwanted reflections from interfering with the exposure of photoresist in subsequent processes. Overlying the DARC is a bottom anti reflective coating layer (BARC) 109. BARC layer 109 is also used to prevent unwanted reflections from interfering with subsequent photoresist processes.
Overlying the BARC layer 109 is a layer of photoresist (PR) 111 that has already been patterned. PR patterning is accomplished by exposure and development to form a pattern for etching. The etch process is selective so that areas protected by the PR are not etched, and areas exposed to the etchant are etched, with the ESL stopping the etching.
In this simple cross section, three via positions 102, 104 and 106 are shown, similar process steps may be used to form trenches, for example, as well as vias. The vias will, when finally completed, be filled with a conductive material and form connections between metal layer 101 and the next metal layer formed above layer 101 in a multiple level metallization scheme as is typically used. For example if copper layer 101 was “metal 1”, then the next metal layer formed above the structure of FIG. 1 would be “metal 2”. If instead, layer 101 were “metal 5” then the next overlying layer of metal would be “metal 6”. Modern semiconductor processes may have as few as one metal layer and possibly many more metal layers. The vias are used to electrically couple the conductors on different layers by forming vertical connections through the dielectric layers.
FIG. 2 depicts the structure of FIG. 1 following additional processing steps. In FIG. 2 the vias (alternatively, trenches) 102, 104 and 106 are shown etched through the DARC layer 107 and the dielectric layer 105 to the ESL layer 103. Etching is well known in the art and typical processing steps may be used such as RIE and plasma etch processes. Wet and dry etch may be used.
FIG. 3 depicts the structure of FIG. 2 following still more processing steps. In FIG. 3, sacrificial plug material is used to fill the vias 102, 104 and 106. This via fill material will be removed later and is provided to protect the sidewalls and bottom of the low-K via hole structure. An etch back step is performed to remove some of the via fill material at the top of the vias adjacent DARC layer 107. In this manner, the DARC layer may be thinned or etched to reduce the thickness of the DARC layer.
FIG. 4 depicts in two views the structure of FIG. 3 following additional processing steps. In FIG. 4, the upper portion depicts a plan view of the vias 102, 104 and 106 and the conductor trenches 117 being formed for the metal trenches Mx. The metal layer Mx could be any metal layer overlying a previous metal layer, (for example metal layer 7 would be M7) and will typically be formed using dual damascene or single damascene processes, with copper deposited in the vias and the trenches overlying the vias, and then a copper metal polishing (CMP) step to remove excess material from the conductor regions to complete both the vias and the overlying conductors.
In the lower portion of FIG. 4 the cross section taken along the dashed line A-A′ through the via portions 102, 104 and 106 is shown. A second BARC layer 110 is now provided overlying the structure and adjacent the DARC layer 107. A second layer of PR 112 is provided and patterned to set up the removal of the via filler 113 by another etch step to complete the vias.
FIG. 5 depicts the completed vias 102, 104 and 106 in the structure of FIG. 4 after additional processing steps. The second PR layer 112, and the second BARC layer 110 are removed following the etch process to remove material 113 from the vias. As can be seen, the tops of the vias 102, 104 and 106 are rounded and sloped. The shape is due to the etch processes which damage the DARC film 107 and the top portions of the dielectric layer 105 within the via regions 102, 104 and 106. This etch damage causes non uniform spacing, lower minimum spacing between the vias, between vias and lines, and line to line spacing.
FIG. 6 depicts in a close up cross section an example via 115 produced using the conventional processes described above. As can be seen, the sides of the dielectric layer 105 and the DARC layer 107 forming the via 115 are sloped to open wider at the top of the via. In the conventional process, the top critical dimension and the etch stop layer will be damaged by the use of the etch processes. Top opening, or bowing profile vias, or even ESL punch through may occur. This can cause “bird beak” effects, for example.
FIGS. 7A and 7B depict actual test structures formed in a conventional semiconductor process using the process steps of FIGS. 1-6. In FIG. 7A, a pair of vias is shown in a SEM photograph looking down on via structures from above. The via shapes can be seen to be elongated near the center. In FIG. 7B, a SEM of the overlying conductors formed on the vias of FIG. 7A is shown in a SEM photo. The minimum spacing between lines formed over these vias is shown to be 21 nanometers, less than the desired minimum spacing. This minimum spacing design violation is due to the irregular shaped opening at the top of the vias. The design parameters are not being met in this example, as the etch process is causing the spacing to change.
One disadvantage of the prior art is that the known approaches to improving the TDDB and via shape post etch problems also have disadvantages. The PR trimming and CD shrinkage of deposition mode in etching processes used in the prior approaches tend to induce additional profile damage. CD uniformity control will then be worse than if these techniques were not used.
A second disadvantage of the prior art is that the various approaches add complexity to the semiconductor processing and thus tend to increase cost and process time. In spite of the additional steps, the photolithography processes tend to limit the advance of semiconductor processing. A continuing need thus exists for semiconductor process methods to improve the TDDB reliability, maintain CD uniformity, and maintain via to via, via to line, and line to line spacing parameters in the semiconductor devices produced, with low cost and without the disadvantages of the known solutions used in the prior art.